PROCESSING SPECIFICATIONS Batch Size: from 40 cm2 to 1000s Mask: according to design rules, and can be printed by customer or Graphenea Graphene growth, transfer, processing and dicing under one roof Metallization: Cr/Au as standard. Optional wetting layers: Ni, Ti. Optional contact layers: Al, AuPd Encapsulation: polymeric, ALD Al2O3 or ALD Al2O3 +Si3N4 Minimum feature size: 5 ¼m Dicing Get in touch for a quote QUALITY CONTROL All our samples are subjected to a rigorous QC in order to ensure a high quality products. Raman Spectroscopy inspection Optical Microscopy inspection Electrical conductivity on test structures

TYPICAL SPECIFICATIONS Growth method: CVD synthesis Chip dimensions: 10 mm x 10 mm Chip thickness: 675 Number of GFETs per chip: 27 Gate oxide thickness: 90 nm Gate oxide material: SiO2 Dielectric Constant of the SiO2 layer: 3.9 Resistivity of substrate: 1-10 ohm cm Metallization: Chromium/Gold 5/45nm Graphene field-effect mobility: >1000 cm2/V.s Dirac point: <50 V Minimum working devices: >75 % ABSOLUTE MAXIMUM RATINGS Maximum gate-source voltage: ± 50 V Maximum temperature rating: 150 °C Maximum drain-source current density 107A.cm-2

TYPICAL SPECIFICATIONS Growth method: CVD synthesis Chip dimensions: 10 mm x 10 mm Chip thickness: 675 Number of GFETs per chip: 36 Gate oxide thickness: 90 nm Gate oxide material: SiO2 Dielectric Constant of the SiO2 layer: 3.9 Resistivity of substrate: 1-10 ohm cm Metallization: Chromium/Gold 2/50nm Graphene field-effect mobility: >1000 cm2/V.s Dirac point: <50 V Minimum working devices: >75 % ABSOLUTE MAXIMUM RATINGS Maximum gate-source voltage: ± 50 V Maximum temperature rating: 150 °C Maximum drain-source current density 107A.cm-2

TYPICAL SPECIFICATIONS Growth method: CVD synthesis Chip dimensions: 10 mm x 10 mm Chip thickness: 675 m Number of GFETs per chip: 31 Gate oxide thickness: 90 nm Gate oxide material: SiO2 Dielectric Constant of the SiO2 layer: 3.9 Resistivity of substrate: 1-10 ohm cm Metallization: Chromium/Gold 5/45nm Graphene field-effect mobility: >1000 cm2/V.s Dirac point: <50 V Minimum working devices: >75 % ABSOLUTE MAXIMUM RATINGS Maximum gate-source voltage: ± 50 V Maximum temperature rating: 150°C Maximum drain-source current density 107A.cm-2

TYPICAL SPECIFICATIONS Growth method: CVD synthesis Chip dimensions: 10 mm x 10 mm Chip thickness: 675 Number of GFETs per chip: 36 Gate oxide thickness: 90 nm Gate oxide material: SiO2 Resistivity of substrate: 1-10 ohm cm Metallization: Chromium/Gold-Palladium 2/50 nm Graphene field-effect mobility: >1000 cm2/V.s Encapsulation: 50 nm Al2O3 + 100 nm Si3N4 Dirac point (back gating): <50 V Dirac point (liquid gating): <1V Minimum working devices: >75 % ABSOLUTE MAXIMUM RATINGS Maximum gate-source voltage:± 50 V Maximum temperature rating: 150°C Maximum drain-source current density 107A.cm-2